- A NAND gate can be considered as an AND gate followed by a NOT gate.
- Aliasing is a desired factor in sampling.
- Two cascaded decade counters divide the clock frequency by 10.
- MIPS stands for memory instructions per second.
- Delta modulation is based on the difference of two successive samples.
- To achieve a modulus of 100, ten decade counters are required.
- A serial shift register accepts one bit at a time on a single line.
- Two types of SPLDs are
- If the present state is 1000, the next state of a 4-bit up/down counter in the DOWN mode is 0111.
- A 5-bit binary counter has a maximum modulus of
- A counter with four stages has a maximum modulus of sixteen.
- Which one of the following is an example of a counter with a truncated modulus?
- The flip-flop used in a CPLD macrocell can be programmed as a
- A digital signal processing system usually operates in
- The maximum cumulative delay of an asynchronous counter must be
- A BCD counter is an example of
- In a computer, the BIOS programs are stored in the
- A register’s functions include
- Optical storage devices employ
- Aliasing results in
- A 3-bit binary counter has a maximum modulus of
- According to the sampling theorem, the sampling frequency should be
- An op-amp is a linear amplifier which has
- DSPs are typically programmed in
- The output of an exclusive-OR is 0 if the inputs are opposite.
- A ring counter uses one flip-flop for each state in its sequence.
- Once programmed, PLD logic can be changed.
- In Verilog HDL, ~(1010) is (0101), and !(1010) is 0.
- Address multiplexing can reduce the number of pins in the IC package.
- The process of converting an analog value to a code is called quantization.
- Fan-out is the number of similar gates that a given gate can drive.
- One of the major applications of SRAMs is in cache memories in computers.
- To achieve a maximum modulus of 32, sixteen stages are required.
- For transmission, data from a UART is sent in synchronous parallel form.
- A counter with a truncated sequence has less than its maximum number of states.
- A shift register cannot be used to store data.
- Logic simplification is still useful in nowadays FPGA designs.
- Successful approximation is an analog-to-digital conversion method.
- An addition overflows if the addends’ signs are the same but the sum’s sign is different from the addends’.
- A shift register with four stages can store a maximum count of fifteen.
- RAM is used in a computer to store the BIOS (Basic Input/Output System
- Shift registers consist of an arrangement of flip-flops.
- An ADC is an analog data component.
- An analog signal can be converted to a digital signal using sampling.
- The initial statement executes only once, starting from simulation time 0, and may continue with any operations that are delayed by a given number of time units.
- A shift register cannot be used as a time delay device.
- To enter a byte of data serially into an 8-bit shift register, there must be
- The overflow does NOT occur when adding the following 8-bit two’s complement number: 10111111+11011111
- Memory expansion is accomplished by adding an appropriate number of memory chips to the address, data, and control buses.
- With a 1 MHz clock frequency, eight bits can be parallel entered into a shift register
- With a 100 kHz clock frequency, eight bits can be serially entered into a shift register in
- The Johnson counter is a special type of shift register.
- The bit capacity of a memory that has 512 addresses and can store 8 bits at each address is
- Data are stored in a random-access memory (RAM) during the
- The output of a Mealy machine depends on its
- The initial count of a modulus-13 binary counter is
- SRAM, DRAM, flash, and EEPROM are all
- In a functional simulation, the user must specify the
- A 16-bit word consists of
- A digital voltmeter uses a
- A 4-bit ripple counter consists of flip-flops that each have a propagation delay from clock to Q output of 12 ns. For the counter to recycle from 1111 to 0000, it takes a total of
- The quantization process
- A byte-organized memory has
- The basic elements of an FPGA are
- Nonvolatile FPGAs are generally based on
- A memory with 512 addresses has
- The factor that determines the adequacy of a GAL for a logic design is
- A 10 MHz clock frequency is applied to a cascaded counter consisting of a modulus-5 counter, a modulus-8 counter, and two modulus-10 counters. The lowest output frequency possible is
- A modulus-12 counter must have
- The modulus of a counter is
- Generally, an analog signal can be reconstructed more accurately with
- A ROM is a
- Three cascaded modulus-10 counters have an overall modulus of
- The group of bits 10110101 is serially shifted (right-most bit first) into an 8-bit parallel output shift register with an initial state of 11100100. After two clock pulses, the register contains
- The ( ) of the A/D converter determines how close the actual digital output is to the theoretically expected digital output for a given analog input.
- A reconstruction filter ( ).
- A higher sampling rate is more accurate than a lower sampling rate for a given analog signal.
- If an anti-aliasing filter is not used in digitizing a signal the recovery process ( )
- Two types of DAC are the binary-weighted input and the R/2R ladder.
- An ADC is an analog data component
- The ( ) of ADC is determined by the number of bits it uses to digitize an input signal.
- The Integral Nonlinearity of an ADC defines the maximum deviation of the ADC transfer function from the best-fit line.
- An anti-aliasing filter should have ( )
- The number of comparators required in a 10-bit flash ADC is ( ).
- Memory expansion is accomplished by adding an appropriate number of memory chips to the address, data, and control buses.
- A 4-bit parallel-in/parallel-out shift register will store data for ( ).
- Static RAM is ( ).
- When data is read from RAM, the memory location is ( ).
- RAM is used in a computer to store the BIOS (Basic Input/Output System.
- The advantage of dynamic RAM over static RAM is that ( ).
- The first step in a read or write operation for a random access memory is to ( ).
- A nonvolatile memory is one that ( )
- An advantage of a ring counter over a Johnson counter is that the ring counter ( ).
- Assume the clock for a 4-bit binary counter is 80 kHz. The output frequency of the fourth stage (Q3) is ( ).
- A possible sequence for a 4-bit ring counter is ( ).
- A 4-bit binary counter has a terminal count of ( ).
- The maximum modulus of a counter is , where n is the number of stages (flip-flops) in the counter.
- For transmission, data from a UART is sent in synchronous parallel form.
- For counters with unused states, it is necessary to ensure that the circuit eventually goes into one of the valid states so that it can resume normal operation.
- To cause a D flip-flop to toggle, connect the ( ).
- A divide‐by‐N-counter is a counter that goes through a repeated sequence of N states, and it is also known as a modulo‐N counter.
- The output of a D latch will not change if ( ).
- For the J-K flip-flop shown, the number of inputs that are asynchronous is ( ).
- In a Moore model, the outputs of the sequential circuit are not synchronized with the clock.
- The D flip-flop shown will ( ).
- The time interval illustrated is called ( ).
- Assume the output is initially HIGH on a leading edge triggered J-K flip flop. For the inputs shown, the output will go from HIGH to LOW on which clock pulse?
- The advantage of dynamic RAM over static RAM is that ( ).
- The output of the Mealy machine is the value that is present immediately before the active edge of the clock.
- In Verilog HDL, an initial behavioral statement executes only once.
- An asynchronous reset signal will override the clock on a FF.
- The continuous assignmentassign OUT = select ? A : B;specifies the condition that OUT = ( ) if select = 1, else OUT = ( ) if select = 0.
- To expand a 2-bit parallel adder to a 4-bit parallel adder, you must ( ).
- The initial statement executes only once, starting from simulation time 0, and may continue with any operations that are delayed by a given number of time units.
- If an hex-to-binary priority encoder has its 0, 3, 6, and 14 inputs at the active level, the active-HIGH binary output is ( ).
- The 74138 decoder can also be used as ( ).
- Assume you want to decode the binary number 0011 with an active-LOW decoder. The missing gate should be ( ).
- Consider the initial block in the following:initialbeginA = 0; B = 0;#10 A = 1;#20 A = 0; B = 1;EndThen at t = 30, A is changed to ( ) and B to ( ).
- In Verilog HDL, the definitions of modules are allowed to be nested.
- The value z represents an unknown logic value in Verilog HDL.
- SOP standard form is useful for constructing truth tables or for implementing logic in PLDs.
- Adjacent cells on a Karnaugh map differ from each other by
- In synthesis, a netlist will be generated to describe the circuit completely.
- The Boolean equation AB + AC = A(B+ C) illustrates ( )
- The Boolean expression A + 1 is equal to ( ).
- The Boolean expression A . 1 is equal to ( ).
- The associative law for addition is normally written as ( )
- In FPGA design, the step that “maps” the design from the netlist to fit it to a target device is known as "programming".
- A Boolean expression that is in standard SOP form is ( )
- The fractional binary number 0.11 has a decimal value of ( )
- The overflow does NOT occur when adding the following 8-bit two’s complement number:10111111+11011111
- The overflow occurs when adding the following 8-bit two’s complement number: 01011101+00110001
- An example of an alphanumeric code is ( )
- In general, we need at most bits to express the product when multiplying an n-bit number by an m-bit number.
- An example of an unweighted code is ( )
- The number 1100 in BCD is ( )
- The 2’s complement of 1000 is ( )
- For the binary number 10000, the weight of the column with the 1 is ( )
- Two broad types of digital integrated circuits are fixed-function and programmble.
- A category of digital integrated circuits having functions that can be altered is known as fixed-function logic.
- A quantity has continuous value is ( )
- Compared to analog systems, digital systems ( )
- Data are information only in numeric.
- There is an “invalid” region between the input ranges for logic 0 and logic 1
- Verilog HDL is a ( )
- The number of values that can be assigned to a bit are ( )
- The nonrecurring engineering (NRE) cost for an ASIC design is normally low.
- The term bit means ( )
答案:对
答案:错
答案:错
答案:错
答案:对
答案:错
答案:对
答案:PAL and GAL
答案:对
答案:32
答案:对
温馨提示支付 ￥5.00 元后可查看付费内容,请先翻页预览!
