第六章 Registers and Counters：Registers and Counters6.1Shift Registers:Shift Registers[单选题]
6.2HDL for registers:HDL for registers
6.3Asynchronous Counters:Asynchronous Counters
6.4Synchronous Counters:Synchronous Counters
6.5Design of Synchronous Counters:Design of Synchronous Counters
6.6Integrated Circuit Counters:Integrated Circuit Counters
6.7Other counters:Other counters
6.8HDL for counters:HDL for counters
An advantage of a ring counter over a Johnson counter is that the ring counter ( ).
, has more possible states for a given number of flip-flops
, is self-decoding
, is cleared after each cycle
]
[单选题]
A possible sequence for a 4-bit ring counter is ( ).
, … 1111, 1110, 1101 …
, … 1000, 0100, 0010 …
, … 0000, 0001, 0010 …
]
[单选题]For counters with unused states, it is necessary to ensure that the circuit eventually goes into one of the valid states so that it can resume normal operation.
选项:[错, 对]
[单选题]A divide‐by‐N-counter is a counter that goes through a repeated sequence of N states, and it is also known as a modulo‐N counter.
选项:[对, 错]
[单选题]
To cause a D flip-flop to toggle, connect the ( ).
, Q output to the D input
,
, clock to the preset input]
[单选题]The maximum modulus of a counter is , where n is the number of stages (flip-flops) in the counter.
选项:[对, 错]
[单选题]For transmission, data from a UART is sent in synchronous parallel form.
选项:[错, 对]
[单选题]A 4-bit binary counter has a terminal count of ( ).
选项:[16, 4, 10, 15]
[单选题]
Assume the clock for a 4-bit binary counter is 80 kHz. The output frequency of the fourth stage (Q3) is ( ).
, 320 kHz
, 10 kHz
, 5 kHz
]
[单选题]A 4-bit parallel-in/parallel-out shift register will store data for ( ).
选项:[2 clock periods
, 3 clock periods
, 4 clock periods
, 1 clock period
]
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