第四章 Combinational Logic：Combinational Logic4.1Analysis of Combinational Logic:Analysis of Combinational Logic[单选题]Consider the initial block in the following:
4.2Design of Combinational Logic:Design of Combinational Logic
4.3Adders:Adders
4.4Subtractor:Subtractor
4.5Multiplier:Multiplier
4.6Decoder:Decoder
4.7Encoder:Encoder
4.8Multiplexer:Multiplexer
4.9Experiment:Experiment
initial
begin
A = 0; B = 0;
#10 A = 1;
#20 A = 0; B = 1;
End
Then at t = 30, A is changed to ( ) and B to ( ).
, 0,1
, 1, 1
, 0, 0
]
[单选题]In Verilog HDL, the definitions of modules are allowed to be nested.
选项:[错, 对]
[单选题]The initial statement executes only once, starting from simulation time 0, and may continue with any operations that are delayed by a given number of time units.
选项:[对, 错]
[单选题]If an hex-to-binary priority encoder has its 0, 3, 6, and 14 inputs at the active level, the active-HIGH binary output is ( ).
选项:[0110
, 0011
, 0000
, 1110
]
[单选题]The continuous assignmentassign OUT = select ? A : B;specifies the condition that OUT = ( ) if select = 1, else OUT = ( ) if select = 0.
选项:[ 0,1
, 1, 0
, B, A
, A, B
]
[单选题]In Verilog HDL, ~(1010) is (0101), and !(1010) is 0.
选项:[对, 错]
[单选题]The value z represents an unknown logic value in Verilog HDL.
选项:[错, 对]
[单选题]The 74138 decoder can also be used as ( ).
选项:[ an encoder
, none of the above
, a DEMUX
, a MUX
]
[单选题]To expand a 2-bit parallel adder to a 4-bit parallel adder, you must ( ).
选项:[use two 2-bit adders with no interconnections
, use four 2-bit adders with no interconnections
, use two 2-bit adders and connect the sum outputs of one to the bit inputs of the other
, use two 2-bit adders with the carry output of one connected to the carry input of the other
]
[单选题]Assume you want to decode the binary number 0011 with an active-LOW decoder. The missing gate should be ( ).
选项:[an OR gate, an AND gate
, a NOR gate
, a NAND gate
]
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