Digital Logic Circuits 数字逻辑电路 第三章_智慧树知到答案2021年

第三章 Boolean Algebra and Gate-level Minimization：Boolean Algebra and Gate-level Minimization3.1Boolean Algebra:Boolean Algebra
3.2Standard Forms of Boolean Expressions:Standard Forms of Boolean Expressions
3.3Minimization and Karnaugh Maps:Minimization and Karnaugh Maps
3.4Introduction to CAD tools:Introduction to CAD tools
3.5Introduction to Verilog:Introduction to Verilog

[单选题]Adjacent cells on a Karnaugh map differ from each other by

选项:[three variables
,  one variable
, two variables
, answer depends on the size of the map
]
[单选题]SOP standard form is useful for constructing truth tables or for implementing logic in PLDs.

选项:[对, 错]
[单选题]Logic simplification is still useful in nowadays FPGA designs.

选项:[对, 错]
[单选题]A Boolean expression that is in standard SOP form is (     )

选项:[contains only one product term
, none of the above
, has every variable in the domain in every term
, the minimum logic expression
]
[单选题]The associative law for addition is normally written as (     )

选项:[A + AB = A
, A + B = B + A
, AB = BA
,  (A + B) + C = A + (B + C)
]
[单选题]The Boolean expression A + 1 is equal to (     ).

选项:[A, 0, B, 1]
[单选题]The Boolean expression A ^. 1 is equal to (     ).

选项:[0, A
, 1, B]
[单选题]In FPGA design, the step that “maps” the design from the netlist to fit it to a target device is known as "programming".

选项:[错, 对]
[单选题]In synthesis, a netlist will be generated to describe the circuit completely.

选项:[对, 错]
[单选题]The Boolean equation AB + AC = A(B+ C) illustrates (     )

选项:[DeMorgan’s theorem
,  the commutative law
,  the associative law
, the distribution law
]