Digital Logic Circuits 数字逻辑电路 第五章_智慧树知到答案2021年

第五章 Sequential Logic：Sequential Logic5.1S-R Latch:S-R Latch
5.2Gated Latch:Gated Latch
5.3Flip-flops:Flip-flops
5.4Synchronous sequential circuits:Synchronous sequential circuits
5.5Using Storage Elements with Verilog:Using Storage Elements with Verilog

[单选题]The time interval illustrated is called (     ).

选项:[hold time
, t_PLH
, t_PHL
, set-up time
]
[单选题]

The advantage of dynamic RAM over static RAM is that (  ).

选项:[all of the above, it does not require refreshing, it is simpler and cheaper, it is much faster]
[单选题]In a Moore model, the outputs of the sequential circuit are not synchronized with the clock.

选项:[错, 对]
[单选题]The output of the Mealy machine is the value that is present immediately before the active edge of the clock.

选项:[错, 对]
[单选题]In Verilog HDL, an initial behavioral statement executes only once.

选项:[错, 对]
[单选题] The output of a D latch will not change if (     ).

选项:[Enable is not active
, D is LOW
,  the output is LOW
, all of the above
]
[单选题]The D flip-flop shown will ( ).

选项:[reset on the next clock pulse
, set on the next clock pulse
, latch on the next clock pulse
, toggle on the next clock pulse
]
[单选题]Assume the output is initially HIGH on a leading edge triggered J-K flip flop. For the inputs shown, the output will go from HIGH to LOW on which clock pulse?

选项:[4, 1, 2, 3]
[单选题]For the J-K flip-flop shown, the number of inputs that are asynchronous is (     ).

选项:[1, 3, 4, 2]
[单选题]An asynchronous reset signal will override the clock on a FF.

选项:[对, 错]